Module es8311 

Everest ES8311 mono audio codec (one ADC, one DAC) over I²C control.

The driver configures the codec as an I²S slave with 16-bit samples and its internal clock derived from the bit clock (MCLK = BCLK × 8). The host needs no MCLK line, and with 16-bit stereo frames (BCLK = 32 × fs) the codec’s clock registers are the same at every supported rate. Only the host’s I²S clock sets the sample rate.

Power is managed by Mode. Es8311::init leaves the codec in Mode::Off with the DAC muted at its minimum volume, so a fresh codec can never make a sound until the caller explicitly asks for playback.

Register values follow M5Stack’s M5Unified (MIT) and Espressif’s esp-bsp es8311 component (Apache-2.0).

Structs

Es8311

ES8311 driver.

MicGain

Analog microphone pre-amplifier gain, 0–30 dB in 3 dB steps. The codec adds a further +24 dB digital ADC_SCALE (register 0x16 reset value).

Volume

Digital volume: −95.5 dB to +32 dB in 0.5 dB steps (0xBF = 0 dB).

Enums

Mode

Which signal paths are powered.

SampleRate

Sample rates supported with BCLK-derived clocking and 16-bit stereo frames. These are the rates for which Espressif’s coefficient table has an MCLK = 32 × fs entry; lower rates are left out until verified.

Constants

ADDRESS_CE_HIGH

I²C address with CE tied high.

ADDRESS_CE_LOW

I²C address with CE tied low.

CHIP_ID

Values of the CHD1/CHD2 chip-ID registers (0xFD, 0xFE).